SI Analysis of DDR Bus during Read/Write operation transitions by Nitin Bhagwath from Mentor
Straight from Dgcon 2017 - The Main Signal & Power Integrity Event In Israel!
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The Lecture:
Traditionally, the Read and Write operations of (LP)DDRx DQ busses have been analyzed independently.
Transitions from one operation to another have usually been prioritized lower.
At lower speeds, this prioritization might be justified, but at the higher speeds of (LP)DDR4, this comes into question. The SI effects between operations make it very important to simulate at higher speeds.
Such analysis will require methodologies and modeling approaches beyond what has traditionally been practiced.
This paper investigates the conditions under which an (LP)DDR bus’s SI will be impacted by operation transitions and details how to perform simulations to handle such conditions.
The Expert:
Nitin Bhagwath is a Technical Marketing Engineer at Mentor Graphics. He has designed
and architected high-speed systems for Hewlett Packard and Cisco for ten years. He has
been with the high-speed simulation group at Mentor Graphics for four years, where he
advises simulation design on multi-gigabit SerDes signals, power integrity and DDR
memory. Nitin represents Mentor Graphics at the JEDEC memory groups. Nitin has a
bachelors in Electronic Engineering from Bangalore University, an MS in EE from
Purdue University and an MBA from the Indian Institute of Management, Bangalore.
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